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22 lines
352 B
Makefile
22 lines
352 B
Makefile
CC = gcc
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CFLAGS = -Wall -Wextra -g
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LIBS = -lm
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# Get all .c files
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SOURCES = $(wildcard *.c)
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# Generate object file names from source file names
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OBJECTS = $(SOURCES:.c=.o)
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TARGET = shell
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all: $(TARGET)
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$(TARGET): $(OBJECTS)
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$(CC) $(CFLAGS) -o $@ $^ $(LIBS)
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%.o: %.c
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$(CC) $(CFLAGS) -c $< -o $@
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clean:
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rm -f $(OBJECTS) $(TARGET)
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.PHONY: all clean |